Metal Oxide Semiconductor (MOS) devices are used extensively in the design of integrated circuits due to the simplicity of their geometry, very small physical size, and extremely small power dissipation. These attributes permit large scale integration (LSI) in which thousands of MOS transistors are contained in one circuit which occupies only a fraction of a square inch of area.
Despite the advantages recited above, MOS logic gates are often not well suited to applications requiring high speed operation. Such applications are possibly better executed by logic devices implemented in the considerably faster TTL (Transistor-Transistor Logic) or ECL (Emitter Coupled Logic) technologies. Although generally faster, TTL and ECL gates dissipate much more power than MOS logic gates.
To simplify and accelerate the design and development of large scale integrated circuits and very large scale integrated (VLSI) circuits, NCR Corporation, as well as others in the semiconductor industry, have designed libraries of commonly used logic circuit functions. These logic circuit functions, referred to as "cells", can include simple structures such as gates and latches or more complex structures such as RAMs, ROMs and PLAs. In addition, the cells can consist of arrays of logic gates or arrays of "cell macros", logic elements performing higher level logic functions than basic gates. Thereafter in the design of a new integrated circuit the system designer can access the cell library to copy a previously designed and tested circuit which performs a function required by the new integrated circuit under design. The use of cell libraries has substantially reduced the design effort required to design complex components.
One of the recurring requirements for new integrated circuit designs is the need for a high speed flip-flop. There are specific applications where the flip-flop designs currently used in the cell libraries are not fast enough to satisfy customer needs.
A schematic illustration of a typical prior art CMOS (Complementary Metal Oxide Semiconductor) clocked D-type flip-flop is shown in FIG. 1. This schematic diagram appears on page 2-89 of the High Speed CMOS Logic Data Book, Copyright 1987 Texas Instruments Incorporated. The flip-flop includes a master section comprised of transmission gates 10 and 12, NAND gate 14 and negative logic input OR gate 16. The output of the master section, i.e. the output of gate 14, is provided to a slave section including transmission gates 20 and 22, and NAND gate 24 and negative logic input OR gate 26. Gates 16 and 24 could alternatively be represented as NAND gates. The transmission gates are controlled by a clock signal C, a LOW clock signal state causing gates 10 and 22 to be active and gates 12 and 20 to be inactive, and a HIGH clock signal state causing gates 10 and 22 to be inactive and gates 12 and 20 to be active.
Operation of the circuit of FIG. 1 is as follows. Consider that initially the clock is HIGH so that transmission gates 10 and 22 are inactive and transmission gates 12 and 20 are active. The flip-flop will have at its output data from the previous clock cycle. Now when the clock goes LOW, gates 10 and 22 will be actived and gates 12 and 20 will be inactived. Data received at input terminal D will appear complemented at the output of the master section. When the clock thereafter goes HIGH, gates 12 and 20 will be actived and gates 10 and 22 will be inactived. The data state present at the output of the master section will be transferred to the Q output of the flip-flop. One complete clock cycle is required to effectuate the transfer of data from input D to output Q.
Preset (PRE/) and Clear (CLR/) inputs are provided to set or reset the outputs regardless of the level of the D and clock inputs. Note that there is only one data path through the flip-flop and that Q/, is produced by inverting Q. Thus, output Q/ lags output Q by the propagation delay of NAND gate 26.